leim 37 dspi 3 ena 0 leim 35 dspi 4 ena 1 leim 37 gls 0 dspi 0 aclr 0 gls 0 dspi 0 clk 0 gls 1 dspi 1 clk 1 li 0 ax[ 0] bx[ 0] li 1 ax[ 1] bx[ 1] li 2 ax[ 2] bx[ 2] li 3 ax[ 3] bx[ 3] li 4 ax[ 4] bx[ 4] li 5 ax[ 5] bx[ 5] li 6 ax[ 6] bx[ 6] li 7 ax[ 7] bx[ 7] li 8 ax[ 8] bx[ 8] li 9 ax[ 9] bx[ 0] bx[ 9] bx[ 0] li 10 ax[10] bx[ 1] bx[10] bx[ 1] li 11 ax[11] bx[ 2] bx[11] bx[ 2] li 12 ax[12] bx[ 3] bx[12] bx[ 3] li 13 ax[13] bx[ 4] bx[13] bx[ 4] li 14 ax[14] bx[ 5] bx[14] bx[ 5] li 15 ax[15] bx[ 6] bx[15] bx[ 6] li 16 ax[16] bx[ 7] bx[16] bx[ 7] li 17 ax[17] bx[ 8] bx[17] bx[ 8] li 18 ay[ 0] by[ 0] li 19 ay[ 1] by[ 1] li 20 ay[ 2] by[ 2] li 21 ay[ 3] by[ 3] li 22 ay[ 4] by[ 4] li 23 ay[ 5] by[ 5] li 24 ay[ 6] by[ 6] li 25 ay[ 7] by[ 7] li 26 ay[ 8] by[ 8] li 27 ay[ 9] by[ 9] by[ 0] li 28 ay[10] by[10] by[ 1] li 29 ay[11] by[11] by[ 2] l 35 ena[1] l 37 ena[0] aclr[0] li 38 ay[18] by[18] li 39 ? li 40 ? li 41 ? li 42 ? li 43 ? li 44 ? li 45 ? li 46 ? li 47 ? li 48 ? li 49 ? li 50 ? li 51 ? li 52 ? li 53 ? li 54 ? li 55 ? li 56 ay[17] by[17] by[ 8] li 57 ay[16] by[16] by[ 7] li 58 ay[15] by[15] by[ 6] li 59 ay[14] by[14] by[ 5] li 60 ay[13] by[13] by[ 4] li 61 ay[12] by[12] by[ 3] sub_nano negate acc_nload ax:27 ay:27 az:26 bx:18 by:19 bz:18 coef_sel_a:3 coef_sel_b:3 clk:3 aclr:2 ena:3 scanin:27 chainin:64 dftout:1 observable_sub_nadd_regout:1 observable_negate_regout:1 observable_acc_nload_regout:1 observable_load_value_ena_segout:1 observable_systolic_x_regout:1 observable_systolic_y_regout:1 observable_systolic_regout:1 outa:64 outb:37 scanout:27 chainout:64 observable_data_ax_regout:27 observable_data_ax_regout:27 observable_data_az_regout:26 observable_data_bx_regout:18 observable_data_by_regout:19 observable_data_bz_regout:18 observable_coef_sel_a_regout:3 observable_coef_sel_b_regout:3 ENUM_DS_DSP_XDS_DSP_RTL__DSP_MODE:3 109 112 110 0 ind_9x9 1 two_18x19 2 one_27x27 3 sum_of_2_18x19 4 one_18x18_plus_36 ENUM_DS_DSP_XDS_DSP_RTL__DSP_SYSTOLIC_REG_EN:1 134 0 systolic_reg_disabled 1 systolic_reg_enabled ENUM_DS_DSP_XDS_DSP_RTL__DSP_EN_COEF:1 392 0 coef_input_disabled 1 coef_input_enabled ENUM_DS_DSP_XDS_DSP_RTL__DSP_DOUBLE_ACC_EN:1 414 0 double_acc_disabled 1 double_acc_enabled ENUM_DS_DSP_XDS_DSP_RTL__DSP_CASCADE:1 165 0 regular_input 1 cascade_input ENUM_DS_DSP_XDS_DSP_RTL__DSP_DELAY_CASCADE_BY:1 395 0 regular_cascade_input_by 1 delayed_cascade_input_by ENUM_DS_DSP_XDS_DSP_RTL__DSP_DELAY_CASCADE_AY:1 137 0 regular_cascade_input_ay 1 delayed_cascade_input_ay ENUM_DS_DSP_XDS_DSP_RTL__DSP_CHAIN:1 113 0 regular_output 1 chain_output ENUM_DS_DSP_XDS_DSP_RTL__DSP_SIGN_AX:1 136 0 unsigned_value_on_ax 1 signed_value_on_ax ENUM_DS_DSP_XDS_DSP_RTL__DSP_SIGN_AY:1 133 0 unsigned_value_on_ay 1 signed_value_on_ay ENUM_DS_DSP_XDS_DSP_RTL__DSP_SIGN_BX:1 394 0 unsigned_value_on_bx 1 signed_value_on_bx ENUM_DS_DSP_XDS_DSP_RTL__DSP_SIGN_BY:1 391 0 unsigned_value_on_by 1 signed_value_on_by BITVEC_DS_DSP_XDS_DSP_RTL__DSP_COEF_H:144 256 244 232 220 208 196 184 172 160 148 94 82 70 58 46 34 22 10 253 241 229 217 205 193 181 169 157 145 91 79 67 55 43 31 19 7 257 245 233 221 209 197 185 173 161 149 95 83 71 59 47 35 23 11 254 242 230 218 206 194 182 170 158 146 92 80 68 56 44 32 20 8 247 235 223 211 199 187 175 163 151 139 85 73 61 49 37 25 13 1 250 238 226 214 202 190 178 166 154 142 88 76 64 52 40 28 16 4 248 236 224 212 200 188 176 164 152 140 86 74 62 50 38 26 14 2 251 239 227 215 203 191 179 167 155 143 89 77 65 53 41 29 17 5 BITVEC_DS_DSP_XDS_DSP_RTL__DSP_COEF_L:144 514 502 490 478 466 454 442 430 418 406 352 340 328 316 304 292 280 268 511 499 487 475 463 451 439 427 415 403 349 337 325 313 301 289 277 265 515 503 491 479 467 455 443 431 419 407 353 341 329 317 305 293 281 269 512 500 488 476 464 452 440 428 416 404 350 338 326 314 302 290 278 266 505 493 481 469 457 445 433 421 409 397 343 331 319 307 295 283 271 259 508 496 484 472 460 374 436 424 412 400 346 334 322 377 298 286 274 262 506 494 482 470 458 446 434 422 410 398 344 332 320 308 296 284 272 260 509 497 485 473 461 449 437 425 413 401 347 335 323 311 299 287 275 263 BITVEC_DS_DSP_XDS_DSP_RTL__DSP_PRELOAD:6 107 104 97 100 98 101 BITVEC_DS_DSP_XDS_DSP_RTL__DSP_PROGINV:108 513 510 504 507 501 498 492 495 489 486 480 483 477 474 468 471 465 462 456 459 453 450 444 447 441 438 432 435 429 426 342 345 339 336 330 333 327 324 318 321 315 312 306 309 303 300 294 297 291 288 282 285 279 276 255 252 246 249 243 240 234 237 231 228 222 225 219 216 210 213 207 204 198 201 195 192 186 189 183 180 174 177 171 168 84 87 81 78 72 75 69 66 60 63 57 54 48 51 45 42 36 39 33 30 24 27 21 18 ENUM_DS_DSP_XDS_DSP_RTL__DSP_INREG_CTRL_AX:1 162 0 bypassed_ax 1 registered_ax ENUM_DS_DSP_XDS_DSP_RTL__DSP_INREG_CTRL_AY:1 93 0 bypassed_ay 1 registered_ay ENUM_DS_DSP_XDS_DSP_RTL__DSP_INREG_CTRL_AZ:1 90 0 bypassed_az 1 registered_az ENUM_DS_DSP_XDS_DSP_RTL__DSP_INREG_CTRL_BX:1 420 0 bypassed_bx 1 registered_bx ENUM_DS_DSP_XDS_DSP_RTL__DSP_INREG_CTRL_BY:1 351 0 bypassed_by 1 registered_by ENUM_DS_DSP_XDS_DSP_RTL__DSP_INREG_CTRL_BZ:1 348 0 bypassed_bz 1 registered_bz ENUM_DS_DSP_XDS_DSP_RTL__DSP_IDIREG_DEC_CTRL:1 116 0 bypassed_dec 1 registered_dec ENUM_DS_DSP_XDS_DSP_RTL__DSP_IDIREG_PRELOAD_CTRL:1 119 0 bypassed_preload 1 registered_preload ENUM_DS_DSP_XDS_DSP_RTL__DSP_IDIREG_ACC_CTRL:1 115 0 bypassed_acc 1 registered_acc ENUM_DS_DSP_XDS_DSP_RTL__DSP_IDIREG_SUB:1 118 0 bypassed_sub 1 registered_sub ENUM_DS_DSP_XDS_DSP_RTL__DSP_OREG_CTRL:1 99 0 bypassed_oreg 1 registered_oreg ENUM_DS_DSP_XDS_DSP_RTL__DSP_CASCADE_1ST:1 423 0 regular_1st_input 1 cascade_1st_input ENUM_DS_DSP_XDS_DSP_RTL__DSP_PREADDER_EN:2 357 156 0 preadder_disabled 2 preadder_add_mode 3 preadder_sub_mode ENUM_DS_DSP_XDS_DSP_RTL__DSP_DFT:1 376 0 dft_clk_enabled 1 dft_clk_disabled ENUM_DS_DSP_XDS_DSP_RTL__DSP_DFT_TDF:1 367 0 dft_tdf_disabled 1 dft_tdf_enabled ENUM_DS_DSP_XDS_DSP_RTL__DSP_DFT_FOR_OP_CLKCE0_CTRL:1 364 0 dft_itg_disabled 1 dft_itg_enabled ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_SMUX0_CTRL:1 370 0 select_labclk0_for_clk_smux0 1 select_lsim6_for_clk_smux0 ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_CLK_SMUX0:1 273 0 select_uninverted_clk_smux0 1 select_inverted_clk_smux0 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_SMUX1_CTRL:1 368 0 select_labclk1_for_clk_smux1 1 select_lsim8_for_clk_smux1 ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_CLK_SMUX1:1 264 0 select_uninverted_clk_smux1 1 select_inverted_clk_smux1 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_SMUX2_CTRL:1 371 0 select_labclk2_for_clk_smux2 1 select_lsim10_for_clk_smux2 ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_CLK_SMUX2:1 261 0 select_uninverted_clk_smux2 1 select_inverted_clk_smux2 ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_CE0:1 270 0 uninverted_ip_ce0 1 inverted_ip_ce0 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_SMUX0_CE_CTRL:1 361 0 clk_smux0_ce_enabled_with_leim_input 1 clk_smux0_ce_permanently_enabled ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_CE1:1 267 0 uninverted_ip_ce1 1 inverted_ip_ce1 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_SMUX1_CE_CTRL:1 365 0 clk_smux1_ce_enabled_with_leim_input 1 clk_smux1_ce_permanently_enabled ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_CE2:1 258 0 uninverted_ip_ce2 1 inverted_ip_ce2 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_SMUX2_CE_CTRL:1 362 0 clk_smux2_ce_enabled_with_leim_input 1 clk_smux2_ce_permanently_enabled ENUM_DS_DSP_XDS_DSP_RTL__DSP_NCLR0_CTRL:1 356 0 select_labclk3_for_nclr0 1 select_lsim12_for_nclr0 ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_NCLR0:1 12 0 uninverted_nclr0 1 inverted_nclr0 ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_NCLR1:1 15 0 uninverted_nclr1 1 inverted_nclr1 ENUM_DS_DSP_XDS_DSP_RTL__DSP_NCLR1_CTRL:1 359 0 select_labclk4_for_nclr1 1 select_lsim13_for_nclr1 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_CTRL_AX17_0:2 131 125 0 select_clk_smux0_for_ax17_0 1 select_clk_smux2_for_ax17_0 2 select_clk_smux1_for_ax17_0 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_CTRL_AY17_0_AZ17_0:2 130 124 0 select_clk_smux0_for_ay17_0 2 select_clk_smux1_for_ay17_0 1 select_clk_smux2_for_ay17_0 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_CTRL_BX17_0:2 389 383 0 select_clk_smux0_for_bx17_0 1 select_clk_smux2_for_bx17_0 2 select_clk_smux1_for_bx17_0 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_CTRL_BY17_0_BZ17_0:2 388 382 0 select_clk_smux0_for_by17_9 1 select_clk_smux2_for_by17_9 2 select_clk_smux1_for_by17_9 ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_CTRL_DYNAMIC_CONTROL_INPUTS:2 106 103 0 select_clk_smux0_for_dynamic_control_inputs 1 select_clk_smux2_for_dynamic_control_inputs 2 select_clk_smux1_for_dynamic_control_inputs ENUM_DS_DSP_XDS_DSP_RTL__DSP_CLK_CTRL_OPREG:2 358 355 0 select_clk_smux0_for_opreg 1 select_clk_smux2_for_opreg 2 select_clk_smux1_for_opreg ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_DEC:1 3 0 uninverted_dec 1 inverted_dec ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_PRELOAD:1 0 0 uninverted_preload 1 inverted_preload ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_ACC:1 6 0 uninverted_acc 1 inverted_acc ENUM_DS_DSP_XDS_DSP_RTL__DSP_PGM_INVERT_FOR_SUB:1 9 0 uninverted_sub 1 inverted_sub ENUM_DS_DSP_XDS_DSP_RTL__DSP_PARTIAL_RECONFIG:1 373 310 448 0 partial_reconfig_disabled 7 partial_reconfig_enabled