M68000
External bus control
Bus arbitration state machine
| Inputs | Outputs |
|---|
| state | bg | in-use | br | bgack | state | bg |
|---|
| 1 | 1 | - | 1 | 1 | 1 | 1 |
| 1 | 1 | - | 0 | - | 0 | 1 |
| 0 | 0 | - | - | 0 | 1 | 1 |
| 2 | 0 | - | 0 | 1 | 1 | 1 |
| 2 | 0 | - | 1 | 0 | 1 | 1 |
| 0 | 1 | - | 1 | 0 | 0 | 1 |
| 1 | 1 | - | - | 0 | 0 | 1 |
| 3 | 1 | 0 | - | 0 | 0 | 1 |
| 0 | 0 | - | 0 | 1 | 0 | 0 |
| 3 | 0 | - | - | - | 0 | 0 |
| 2 | 0 | - | 0 | - | 2 | 0 |
| 1 | 0 | - | - | - | 2 | 0 |
| 0 | 1 | - | 0 | - | 1 | 0 |
| 3 | 1 | 0 | 0 | 1 | 3 | 0 |
Bus cycle control
Idle
- line 2 on (544), everything else off
Read step 48 (iclk 0.75)
- 9701 = !(9629 || 9697 || 9656) on iclk, change of 9656
- 9656 = !(9633 || (9644 && 9591) || test_mode_active), change on 9591
- 9591 = !(test_mode_active || 8975 || (aob_active && !9342) || !(9616 && bus_nowait)), change on aob_active (1 -> 0)
- aob_active controlled by latched nano 63&64
Read step 49 (clk 1)
- 10058 = !(bus_in_use || 10003) (latching loop)
- line 3 (bus_in_use) on (532) everything else off
- Inversion of control line 1 (4796/4806)
- Latch on clk of line 9701 to control 1
Read step 50 (clk 1.25)
No change
Read step 51 (iclk 1.5)
- 9720 = !(10058 || 9611 || 9618(unlatched)) latch on iclk
Read step 52 (iclk 1.75)
No change
Read step 53 (clk 2)
- 9917 (control line 4 pre) = !(9631 (line 7) || 9635 (latching loop))
- bus_in_use back to 0, 10058 stays 0 due to latch/loop on clk/9720
- 9603 (delay line start) = !(9631 (line 7) && 9630 (line 1))
- line 7 (9631) on, everything else off
- Inversion of control line 2
- Latch on clk on line 9720 to control 2