class HDMIFB(Elaboratable):
    def __init__(self):
        self.o_rd_data = Signal(32)
        self.i_rd_adr  = Signal(16)

        self.ram_adr = [Signal(9) for _ in range(128)]
        self.ram_vadr = [Signal(9) for _ in range(128)]
        self.ram_datain = [Signal(32) for _ in range(128)]
        self.ram_dataout = [Signal(32) for _ in range(128)]
        self.ram_vdataout = [Signal(32) for _ in range(128)]
        self.ram_selectw = [Signal(1) for _ in range(128)]
        self.ram_selectr = [Signal(1) for _ in range(128)]
        self.ram_vselectr = [Signal(1) for _ in range(128)]
        self.ram_byteena = [Signal(4) for _ in range(128)]
                
        self.bus = wishbone.Interface(addr_width = 16, data_width = 32, granularity = 8, name="videoram")
        map = memory.MemoryMap(addr_width = 18, data_width=8, name="videoram")
        map.add_resource(self, name="videoram", size=65536*4)
        self.bus.memory_map = map

    def elaborate(self, platform):
        m = Module()

        for i in range(256):
            m.submodules += Instance("altsyncram",
                i_clock0 = ClockSignal("sync"),
                i_clock1 = ClockSignal("ramdac"),
                i_address_a = self.ram_adr[i//2],
                i_address_b = self.ram_vadr[i//2],
                i_data_a = self.ram_datain[i//2][0:16] if (i & 1) == 0 else self.ram_datain[i//2][16:32],
                o_q_a = self.ram_dataout[i//2][0:16] if (i & 1) == 0 else self.ram_dataout[i//2][16:32],
                o_q_b = self.ram_vdataout[i//2][0:16] if (i & 1) == 0 else self.ram_vdataout[i//2][16:32],
                i_wren_a = self.ram_selectw[i//2],
                i_wren_b = C(0),
                i_rden_a = self.ram_selectr[i//2],
                i_rden_b = self.ram_vselectr[i//2],
                i_byteena_a = self.ram_byteena[i//2][0:2] if (i & 1) == 0 else self.ram_byteena[i//2][2:4],
                p_ram_block_type = 'M10K',
                p_intended_device_family = 'CycloneV',
                p_operation_mode = 'BIDIR_DUAL_PORT',
                p_indata_reg_a = 'bypass',
                p_byteena_reg_a = 'bypass',
                p_outdata_reg_a = 'unregistered',
                p_outdata_reg_b = 'unregistered',
                p_byte_size = '8',
                p_widthad_a = '9',
                p_width_a = '16',
                p_width_byteena_a = '2',
                p_widthad_b = '9',
                p_width_b = '16',
                p_width_byteena_b = '2'
                )

        for i in range(128):
            m.d.comb += self.ram_adr[i].eq(self.bus.adr[:9])
            m.d.comb += self.ram_vadr[i].eq(self.i_rd_adr[:9])
            m.d.comb += self.ram_selectr[i].eq((self.bus.adr[9:16] == i) & ~self.bus.we & self.bus.cyc & self.bus.stb)
            m.d.comb += self.ram_selectw[i].eq((self.bus.adr[9:16] == i) & self.bus.we & self.bus.cyc & self.bus.stb)
            m.d.comb += self.ram_vselectr[i].eq(self.i_rd_adr[9:16] == i)
            m.d.comb += self.ram_datain[i].eq(self.bus.dat_w)

            m.d.comb += self.ram_byteena[i].eq(self.bus.sel)

            with m.If(self.ram_selectr[i]):
                m.d.comb += self.bus.dat_r.eq(self.ram_dataout[i])
            with m.If(self.ram_vselectr[i]):
                m.d.comb += self.o_rd_data.eq(self.ram_vdataout[i])
                
        m.d.sync += self.bus.ack.eq(self.bus.cyc & ~self.bus.ack)

        return m